Generally, integrated circuits (ICs) are formed on a wafer in parallel. An IC includes arious circuit components such as memory array, high voltage (HV) devices and high speed logic circuit elements. The wafer is subjected to dicing in order to singulate the devices. Integration of these different types of devices in a single die or chip involves a number of considerations such as, for example, interference which is prone to occur between the different devices. For example, in the case of RF applications where the devices are the path for a signal transmission or reception, the signal integrity is pivotal because it contains information that need to be treated. The devices neighboring each other such as, for example, switches, low noise amplifiers, filters or power amplifiers will generate a surrounding noise that will limit the performance of a system. To ensure proper transmission and reception, the devices therefore need to be well isolated from each other and from the surrounding devices in the overall system. Another consideration is wafer thickness uniformity in conventional processes for forming the devices which affects device performance. As such, there is a need to properly isolate the different types of devices from each other during integration while providing uniform wafer thickness. Conventional isolation techniques used for isolating the different types of devices poses potential breakdown voltage (BV), cross talk, noise and other reliability issues.
From the foregoing discussion, it is desirable to provide reliable and optimized isolation structures to effectively isolate various devices in a wafer with improved wafer thickness uniformity.